The invention relates to an arrangement for the connection of peripheral memory devices.
The currently known solutions for arrangements for the connection of peripheral memory devices to higher-level system units are based on large peripheral memory device subsystems which allow matching to desired values with respect, for example, to performance or failure reliability, with the following basic structure.
The memory devices are combined into sub-blocks via device controllers. Within a sub-block, the memory devices are connected in parallel. The device controllers have a plurality of independent connections or, alternatively, multimaster-compatible ports. The number of devices per sub-block is in this case limited, for various reasons, to about 8 to 16.
In a next controller hierarchy, the sub-blocks are jointly allocated to one or more higher-level system controllers. At this hierarchy level, one or more system connections are available to one or more higher-level system units, for example to host systems.
The number of system controllers operating in parallel is always limited to the maximum available number of device controller ports. Owing to the complexity in terms of hardware and wiring for the device controllers which control the ports, this generally leads to the number of ports, and thus to the number of system controllers as well, being limited to four.
A structure as described above is known, for example, from the European reference EP-A-0 528 060, in particular FIGS. 3 and 5.
A disadvantage of this architecture is that even the smallest basic structure generally has the basic complexity for the multiple connection capability. A further disadvantage is the multi-stage concept which necessitates a high level of hardware complexity, complicates the wiring and limits the performance, that is to say the throughput and the response time. Furthermore, the number of memory devices that can be used and the capability for adaptation to more stringent requirements are limited in terms of the system controllers and the system connections.
International reference WO91/14229 discloses an arrangement for the connection of peripheral memory devices, in particular disk memories, to one or more higher-level system units in a data processing system. The connection is made via at least one intermediate data transmission controller. The data transmission controller has control devices for controlling the data interchange between the memory devices as respective sinks or sources and the higher-level system units. The arrangement is based on a tree-like structure. The higher-level system units are connected to a small number of cross-switches, each of which is connected to all the data transmission controllers. One respective data transmission controller is connected to two memory devices. Admittedly, because of the tree-like structure each system unit can communicate with each memory device. However, an increase in the number of memory devices as a rule involves major intervention in the tree structure, since new cross-switches or additional data transmission controllers must be introduced.